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1. a) You are asked to design a single circuit to implement g = f1-f2 where: f_{1}=w \cdot x^{\prime} \cdot y^{\prime} \cdot z^{\prime}+w \cdot x \cdot y^{\prime} \cdot z+w^{\prime} \cdot

x \cdot y^{\prime} \cdot z f_{2}=w \cdot x \cdot y^{\prime} \cdot z+w^{\prime} \cdot x \cdot y^{\prime} \cdot z^{\prime}+w \cdot x \cdot y^{\prime} \cdot z^{\prime} Constraints: Logic gates with a propagation delay of 2 ns each must be used Circuit output should be obtained within 1 cycle of a 110 MHz clock i) Assuming that w is the msb and z is the Isb, draw a truth table listing the values of f1 and f2 for all possible value combinations of w, x,y and z. ii) Draw a single, simple circuit diagram implementing g using two 8-to-1 MUX and a single AND gate, with w, x and y as select input variables, and z as a data input variable. Explain clearly how to derive the logic of each MUX (one for each function, f1 and f2) from your truth table. iii) Considering the internal logic of an 8-to-1 MUX, can your design in part (ii)satisfy the constraints above? Explain your reasoning, including an appropriate circuit diagram, in less than 50 words. iv) Reverse the order of bit significance of w, x and y in your truth table from 1(a)(i), to clearly show how two 4-to-1 MUX can be used instead of two 8-to-1 MUX. (You should still use z as a data input variable for each MUX.) Explain your reasoning briefly. Draw a new truth table and a simple circuit diagram.Hint: the signal from your new msb should be zero for all logic high outputs of f1 and f2; you should invert this signal and connect it directly to the AND gate,bypassing the two MUX.

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