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capacitance values to allow estimation of frequency response. From HW4, the PMOS transistors

within the diff-amp are designed to have gm-1mA/V at 60 μA. Assume that these transistors

(M1, M2) have capacitances as follows (at 60μA): Cgs = 20e-15 F; Cgd=4e-15 F; Cdb = Csb =

15e-15.The drain resistors are designed at 12 km2.

Both Vinp and Vinn are driven using sinusoidal sources with 500 source resistance on each

side. Assume the outputs are connected to a differential load capacitor of 40 fF. Draw out the

differential-mode half circuit with all of the capacitors and resistors marked, then estimate the

poles of this circuit in the differential mode using

a. Miller's approximation for both dominant and secondary poles

b. The exhaustive approach discussed in lecture for dominant and secondary poles

c. Open-circuit time-constant technique for the dominant pole

d.

Open-circuit time constant technique assuming that Cload is a short circuit. This is a

trick that can be used to estimate the secondary pole when a dominant pole is present

(i.e., for frequencies high above the dominant pole, the large capacitor in the circuit can

be approximated with a short circuit and then you can use Octau technique).

M1

M3

Iner

Vpo

Viro

R₂₁

M5

Fig. 2

M2

M4

Cload

M6

R₂₂

V

Fig: 1