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1-bit FA xschem & LVS

1-bit DFF xschem

stick diagrams of leaf cells

create leaf cells and perform LVS

assembled top-level Magic and perform LVS

ngspice testing

report/n VLSI Design Project

ECEN 4303: Digital Integrated Circuit Design

Fall 2023 Semester

Version 1.0.0*

1 Introduction to Bit Slices

This projects involves an intense project which you will design a 8-bit custom-based datapath slice. If you

get done early, you could integrate some standard-cell parts to fully complete the block as well as other

mathematical computations. Extra credit is available if you fabricate your design which is available to all

who take this class.

Datapath layout is often performed in custom-level cells for several reasons [1]. The datapath is usually

the portion of a circuit that performs the majority of the useful work and contains the circuit's critical path.

Therefore, it is worthwhile to make the datpath as fast as possible. Trained mask designers spend hours

trying to produce dense and efficient layouts that can minimize the delays along a circuit's critical path

or exhibit low power characteristics. The high density is also important to make the layout as compact as

possible, since datapath layout is often repeated. Although the custom portion of this design is not super

critical to the process, the overall idea of the project will give you a sense of what is needed to design

integrated circuits as a whole. It also gives you an idea how custom-level design is critical to target a specific

integrated circuit for speed and/or power.

In this project you will putting together several parts within a custom block, such as an adder, multiplexor,

and register. For this assignment, utilizing a bit slice technique will help you complete the design more

efficiently. Bit-slicing is a popular technique in partitioning designs, so that they are more manageable [1].

This is fairly common in VLSI, since we would like to minimize the amount of time we spend doing custom

level layout because it takes a majority of the time in most designs. A bit-slice involves designing datapath

elements together for one bit and then repeating the cells in the direction of the word slice. Careful attention

to floorplanning and recognizing certain repetitive areas in a cell can lead to good compact designs.

2 Planning Layout

The use of hierarchy within a layout is critical. Many people fail to see the correlation between object-

oriented design and hardware. However, these ideas behind the Object Oriented paradigm are extensively

used within the hardware domain. Re-utilization of layout cells can greatly decrease your overall complexity,

simplify debugging and limit your design time.

Creating diagrams of you design in terms of its hierarchy is also recommended. For example, a full adder

can be made with two xor gates and an or gate. Similarly, an exclusive-or (XOR) gate can be made with

NAND, NOR, and Inverter gates.

*Note that this document is updated periodically to provide you with the most reliable information to complete the project.

Although previous versions of this document are basically correct, frequent revisions are made in order to help you save time

and not to hinder your performance. Therefore, make sure you check back periodically for updates. I will add revision numbers

to help you identify which version of this document you have. In this design, try to keep all the ndiff regions near the GND line and the pdiff regions near the VDD

line. This is because of the need for body contacts. In general, inputs should be on the left and the top sides

of the cells and the outputs should be on the right and the bottom. Make all the cells the same height so

that the VDD and GND lines are continuous when abutment is used. This process of keeping everything a

certain height is called pitch-matching.

2.1 Floorplanning

Just like our layout assignments, without a careful plan on how you actually put together your circuits,

can lead to hours of pain and agony. This is one of the great things about the stick diagram. One of the

ways to extend this to higher level designs, especially designs that utilize hierarchy, is to use floorplanning.

Floorplanning involves the simple diagramming of your circuit and how it gets put together.

As we learned in lecture, a stick diagram may help us to visualize the structure, but it does not help

us with the sizing. You can extend this by using pitch. Pitch is the distance, usually between two metals,

between each layer. There are various ways to measure the pitch, such as between the center of a metal and

its next edge. One way that you can incorporate this into your stick diagrams is to allow a 8 lambda pitch

between each contact. Of course, you will have to account for the minimal width of each diffusion region,

but it can help you with getting the dimensions of each cell.

Once you have a more or less idea of the size of your cell, you can use this to floorplan your layout. When

utilizing hierarchy, certain functions will use each other ostensibly. For example, an AND gate would utilize

an NAND and and inverter gate. How you put them together, would involve high-level floorplanning. In

other words, putting objects or blocks together and placing dimensions together to get an idea of the size

necessary. There may be many times when you have to floorplan your circuit to fit a certain size. Therefore,

the better the floorplan, the better the implementation. An example of a floorplan is shown in Figure 1.

3 Complex Gates

Normally, an XOR gate can be formed by using other functions such as from AND and OR gates. However,

we can use a little trick to help us make the XOR and subsequently, the full adder more robust.

If we look at the basic equations for an xor gate, it is:

y lambda

fxor

w lambda

With some simple applications of DeMorgan's Theorem, the xor gate can be broken into the following:

fxor

(A · B) · (A · B)

(A + B) · (A + B)

A. B+ A.B

This can be easily be built in CMOS using the techniques we utilized during the first part of the semester.

=

=

=

=

x lambda

XOR

A B

NAND

z lambda.

111

||||| |

Vdd

2

Gnd

Vdd

Function 1

Function 2

Figure 1: Sample Floorplan. 3.1 Mirror Circuits

The XOR circuit is one of the most beneficial circuits to design engineers. Not only is it vital to adder

circuits, but it plays a key role in cryptographic circuits, such as parity generation. Therefore, anything that

can be done to speed up this circuits is monumental.

One method of making the XOR circuit more compact and quicker is to use the mirror circuit. The

mirror circuit is basically where the NMOS and the PMOS gates have exactly the same structure. However,

they do not use series-parallel, but use many of the same characteristics (i.e. the mirror does not have any

parallel structures except at the folding point).

3.2 Full Adder

The full adder is the basi cell for most dd

full adder cell are

The origin of the mirror circuit comes from the truth table of the circuit to be designed. For the XOR

gate, it is easy to see that it appears the truth table is flipped as shown in Table 1.

a D

In order to construct the mirror XOR gate, it is necessary to remove the parallel structure for the PUN

group of A B. This is achieved by removing the parallel structure normally found in the XOR gate (i.e.

(Ā · B) + (A · B)) and rewriting the equation. The circuit is shown in Figure 2.

It is important to note that although the basic element of an XOR gate is built-using mirror circuits,

that it still requires inverters. This is a fundamental problem with most circuit styles today and it appeals

strongly to static CMOS design. Other circuit styles such as dynamic CMOS can not easily make an inverted

signal, since dynamic CMOS is non-inverting. Therefore, although dynamic circuits tend to be much faster

than static CMOS circuits, they still need inverters. Most dynamic logic styles in CMOS still utilize the

static CMOS inverter due to is ability to create easy inversions and PMOS' ability to be the "perfect" load.

vdd

A

0

0

1

1

Table 1: XOR Truth table.

1.68

0.15

0.84

0.15

B

0

1

0

1

gnd

Sum

Cout =

=

Because the full adder is basically counting whether or not one value is above a certain level, the full adder

is typically called a (3, 2) counter. This is because there are 3 inputs and 2 outputs.

Similar to the XOR gate, the full adder can utilize a mirror structure as seen by the full adder's truth

table. Although Cin does not appear to have any mirrored structure, it is clearly evident that Sum does.

implementations. The basic equations for addition using the

A B Cin

A. B+ Cin (A + B)

ad[

XOR

0

1

1

0

1.68

0.15

1.68

0.15

0.84

0.15

0.84

0.15

vdd

gnd

3

1.68

0.15

1.68

0.15

0.84

0.15

0.84

0.15

]p-ab

-D out

a

b

vdd

1.68

0.15

0.84

0.15

gnd

Figure 2: XOR Function Using Mirror Circuits.

b CD

d[

0.42

0.15

0.42

0.15

vdd

b D

0.42

0.15

0.42

0.15

b

gnd

0.42

0.15

0.42

0.15

a D

b D

b D

a D

vdd

0.42

0.15

0.42

0.15

0.42

0.15

0.42

0.15

gnd

a

d

0.42

0.15

0.42

0.15

b D

b D

vdd

0.42

0.15

0.42

0.15

0.42

0.15

0.42

0.15

gnd

4

CD

c

0.42

0.15

0.42

0.15

a

c

bood[

cod[

b

vdd

ad[

Figure 3: (3,2) Counter Function Using Mirror Circuits.

0.42

0.15

0.42

0.15

0.42

0.15

0.42

0.15

0.42

0.15

0.42

0.15

gnd

sum

-D cout

The circuit is shown in Figure 3. Again, careful use of an inverter is needed as shown in the diagram.

The Full Adder is made from the 28 transistor Full Adder cell. You may also add specific logic to

perform either a logic addition or subtraction. This is easily accomplished in most processors by utilizing

an exclusive-or (xor) on the second input operand. Normally, a bit signal can be used to to indicate either

two's complement addition or subtraction.

Subtraction is the same as addition except we add the negative version of a given operand. That is,

instead of adding b + a, the operation is able to subtract a from b by complementing a (i.e. b+ (−a)) via a

subtract signal. Since this project will utilize two's complement addition/subtraction, your project must be

able to add the magic one or unit in the last position (ulp), because it is a radix-complement of the binary

system. Therefore, the adder will calculate b + −a +ulp [2]. An ulp is an acronym that signifies the unit

in the last place [3]. This terminology is the correct method of describing adding one to the number, since

we do not know if the number is an integer or a fraction. For the remainder of this project definition, the

phrase ulp will be utilized.

This year we will give you the mirror adder circuit, but you will need to LVS it to make sure it works.

It is also adviable to utilize this cell to help craft the register design. Since the register cell will probably be

larger, it is advisable to be careful on how you design this circuit.

3.3 Registers

Building registers in one of most crucial elements that exists in any datapath design. This is because they

are crucial to storing data and re-using it for future use. Therefore, having efficient, low-latency, minimal

area design is important for any design. In this section, you will implement a register that will follow your

adder.

The fundamental building block of a d flip flop is the d or transparent latch. And there are many

approaches for constructing latches. One very common technique involves the use of transmission gate mul-

tiplexers. Multiplexer-based latches can provide similar functionality to the SR latch, but has the important

added advantage that the sizing of devices only affects performance and is not critical to the functionality.

Some systems use Static Random Access Memory (SRAM) to build registers, however, we are going to

simplify things. To make things easier, you will be implementing a complete D flip-flop, similar to the Full

Adder design. A better and easier design that you can use for this project is shown in Figure 4. Although

hierarchical designs can sometimes be better for more structured gates, some gates, such as the D-flip-flop,

are better when they are structured as an individual gate. Ultimately, circuit-level simulation is best suited to

adequately determine the objective in which to optimize a gate. Figure 4 shows the schematic representation DD

1.68

0.84

0.15

CIK B

0.42

0.15

0.42

and

0.42

0.15

0.15

E I I FEET

0.15

042

015

AA

diffpos.cit Scale: 0.233645 (5935X)

n

0000

I

1

GR

h

0.15

0.15

0.42

0.15

Figure 4: Transistor Level Schematic of a Positive D flip-flop Using Transmission Gates.

5

0.42

0.15

and

0.42

0.15

0

0.42

0.42

0.15

TR

0.42

0.15

Figure 5: Sample Transistor Gate Implementation of a Positive D flip-flop Using Transmission Gates.

and Figure 5 shows a sample layout previously done by the author of this project (to help you with the

floorplanning).

Sequencing elements, such as a d flip flop, also often accept an enable input. When enable is low, the

element retains its state independently of the clock. The enable can be performed with an input multiplexer

or clock gating, as shown in Figure 6. The input multiplexer feeds back the old state when the element

is disabled. The multiplexer adds area and delay. Clock gating does not affect delay from the data input

and the AND gate can be shared among multiple clocked elements. Moreover, it significantly reduces power

consumption because the clock on the disabled element does not toggle. However, the AND gate delays

the clock, potentially introducing clock skew. You can also addresses techniques to minimize the skew by

building the AND gate into the final buffer of the clock distribution network. however, the enable must be

stable while the clock is high to prevent glitches on the clock.

3.4 Bitslicing

This project's task is simple and two-folded. The main task is for you to understand the importance of

bit-slicing and the second is to work on integrating many of the ideas you had throughout the semester into

one package or learning experience. The bad part about this is that it will involve you to task your time

throughout the semester or you will not have enough time to complete this project. Therefore, please pay

attention to time milestones when working on this project.

The bitslicing project will involve a portion of a design based on simple computation. This part could be

utilized to implement a chip that can compute any function, similar to what is found on a typical datapath

Fig: 1