[20 minutes] 7.1 [17 points] +1.5 V (b) If the gate width is doubled but the value of [5 points] Voy is maintained, what do the values of Ip. gm> and ro become? Figure 7.1.1 GS The NMOS transistor in the circuit in Fig. 7.1.1 has μn Cox = 0.4mA/V2, W/L = 25, and V₁ = 0.4 V. [3 points] (a) Find the value of VGs that results in saturation- mode operation with a dc current of 0.1 mA. Neglect the Early effect. [2 points] (b) Find the value of Rp that results in a de drain voltage of 0.5 V. [4 points] (c) Find gm and ro at the dc operating point specified above. Assume V=5V. [3 points] (d) Find the open-circuit voltage gain Avo [5 points] (e) If a sinusoidal signal with peak amplitude Vi is superimposed on the de voltage VGS, find the maximum allowable value of V; for which the transistor operates in saturation. [15 minutes] 7.2 [12 points] An NMOS transistor fabricated in a 0.18-μm CMOS technology has L = 0.54 μm and W = 10.8 μm. The technology is specified to have HnCox 400 μA/V2, Vin = 0.5V, and 4 = 5 V/μm. [7 points] (a) If the device is operated in saturation with an overdrive voltage of 0.2 V, find the required values of ID and VGS, along with the resulting values of gm and ro. 7.3 [35 minutes] A 0.18-um CMOS technology is specified to have [35 points] n = 450 cm²/V-s, p = 100 cm²/V-s, Cox = 8.6 fF/m², Vin-Vip = 0.5 V, and de power supply of 1.8 V. (a) Find the transconductance parameters K, and [4 points] Kexpressed in μA/V². (b) Find the W/L ratios of matched NMOS [6 points] and PMOS transistors that exhibit resistance rps of 250 when operated in the triode region with an overdrive voltage of 0.3 V. If twice-the- minimum channel length is used, specify the width of the NMOS transistor and the PMOS transistor. (c) If the devices in (b) are operated in saturation [8 points] with Vor 0.2 V, what drain current results? If for each transistor the source is connected to ground, what should the gate voltages be? In each case, specify the range of voltages permit- ted at the drain for saturation-mode operation to be maintained. (d) If the drain currents in (c) are to be reduced [5 points] by a factor of 4, what should the overdrive voltage be? If instead of changing Vorl, the IC designer redesigns the widths of the transistors, what W values would be required? (e) If the devices described in (b) above are oper- [2 points] ated in saturation with Vorl = 0.2 V, find the resulting value of gm. (f) If an NMOS transistor as in (e) above is con- [5 points] nected as a common-source amplifier with RD = 5 kQ and VDD = 1.8 V, what de voltage would appear at the drain? What small-signal voltage gain A,, would be obtained? (g) Recalculate the voltage gain in (f) taking into [5 points] account channel-length modulation. Assume the 7-1 Sedra | Examination Questions for Microelectronic Circuits, Eighth Edition Ⓒ Oxford University Press 2020

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