[25 minutes] 8.4 [15 points] VDD Q2 8.5 55 Q2 +1.8 V R [20 minutes] [14 points] Figure 8.4.1 The cascode current source in Fig. 8.4.1 utilizes two identical PMOS transistors fabricated in a 0.18-μm CMOS process for which VDD = 1.8 V, Vip = -0.5 V, V-6 V/um, and pCox = 100 μA/V². Design the circuit to obtain = 50 μA and Ro=1 MQ and to allow for the maximum pos- sible voltage swing at the output terminal of the current source. Utilize |Vorl= 0.2 V. Specify the values of L and W/L for Q1 and Q2. As well, spec- ify the required values of the de bias voltages VGI and VG2. What is the maximum allowable voltage at the output? Figure 8.5.1 The modified Wilson current mirror of Fig. 8.5.1 utilizes four matched transistors for which V₁ = 0.4V, Cox = 400 μA/V2, and VA =3V. It is required to design the circuit so that Io= 0.2 mA with all transistors operating at Voy = 0.2 V. (a) Find the required value of R. [4 points] (b) Find the required value of the W/L ratio for [3 points] each of the four transistors. (c) Find the value of the output resistance Ro. [4 points] (d) What is the minimum voltage permitted at the [3 points] output?

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