Question
3. Consider a plant G(s) 2 Design a controller K(s) for it with the following specifications. (s+2)(s+1) • % overshoot in the step response y(t) is less than 5% • • Settling time of the step response y(t) is less than 6 seconds. For a unit ramp reference input, the steady state error must be less than 0.12. Write down
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