[30 minutes] 9.9 130 points] 2 REF=200 JAA" Figure 9.9.1 Vao +1 V -Vs--IV 2000 The two-stage CMOS op amp shown in Fig. 9.9.1 is fabricated in a 0.18-um technology having = 4k 400 μA/V2, and Vin = -Vp=0.4 V. [12 points] (a) With A and B grounded, perform a de design that will result in each of Q1, Q2, 23, and Q4 conducting a drain current of 100 μA, and cach of Qs. 26, and Q conducting a drain current of 200 μA. Design so that all transistors operate at a 0.2-V overdrive voltage. Neglect the Early effect. Specify the W/L ratio required for each MOSFET Present your results in a table. What is the de voltage at the output (ideally)? (b) Find the input common-mode range. [6 points] (c) Find the allowable range of the output voltage. [4 points] (d) With 4/2 and up/2, find the [8 points] voltage gain / Assume that the Early voltage is V-5V. 9.10 Refer to Figure 9.10.1 below. Note: Neglect [38 minutes] the Early effect; that is, assume rooo. Assume [28 points] VBE-0.7 V (a) For V = Vg = 0V and neglecting all base [10 points] currents, design the circuit of Fig. 9.10.1 so that each of Q1 and Q2 operates at a de bias current. of 0.25 mA, Vc=VD=+10 V, Vg=0V, and Qs operates at a de bias current of 3 mA. Specify the de bias current at which each of Q3 and Q4 will be operating and give the required value of R1, R2, R3, R4, and Rs. (b) If ẞ=99, what must the value of each of the [3 points] two resistances labeled Re be so as to obtain an input differential resistance of 40 k? (c) Find the differential voltage gain of the input [5 points] stage, 01-02 (d) Find the voltage gain of the second stage, [5 points] 03-04 (e) Find the voltage gain of the output stage, Qs. (f) Find the overall voltage gain, ve/(-va). [3 points] [2 points] x1 +15 V R₂ Ao- Qz B x1 x2 Re R₁ x1 -15 V Figure 9.10.1 -OE

Solved: [30 minutes] 9.9 130 points] 2 REF=200 JAA" Figure 9.9.1 Vao +1 V -Vs-

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30 minutes 9 9 130 points 2 ref 200 jaa figure 9 9 1 vao 1 v vs iv 200

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[30 minutes] 9.9 130 points] 2 REF=200 JAA" Figure 9.9.1 Vao +1 V -Vs--IV 2000 The two-stage CMOS op amp shown in Fig. 9.9.1 is fabricated in a 0.18-um technology having = 4k 400 μA/V2, and Vin = -Vp=0.4 V. [12 points] (a) With A and B grounded, perform a de design that will result in each of Q1, Q2, 23, and Q4 conduct