5. [10 pts] A D flip-flop has a setup time of 7ns, a hold time of 4ns, and a propagation delay from the rising edge of the clock to the change in flip-flop output in the range of 7 to 9ns. An OR gate delay is in the range of 2.5ns to 3.5 ns. What is the minimum clock period for proper operation of the following circuit? D Q DO Cik

Fig: 1