7-3 [40 minutes] 7.6 [32 points] his Vcc +12 V Rai R R RL voltage divider of IE/10. What values are required for Rg1, R2, Rg, and Rc? (b) If the transistor has = 100, find the actual [6 points] values obtained for IE, IC, VB, and VC- (c) What are the values of go, re, and rx at the de [3 points] bias point. (d) Assuming very large coupling and bypass [4 points] capacitors, find the values of Rg and Rez that result in Rin 10 k2. (e) Find the overall voltage gain Gym/ig [6 points] (f) For 1, a sine wave with a 1-V peak ampli- [7 points] tude, what is the peak amplitude required of the sine wave ? If this value is greater than 5 mV, reduce sig to limit the peak amplitude of the to 5 mV. What is the resulting output voltage in this case? R R R R Figure 7.6.1 == RE C == = R 10 kn R-10 k [6 points] (a) Perform a de bias design for the amplifier in Fig. 7.6.1. For this purpose, assume is very high and VBE 0.7 V and neglect the Early effect. Design to obtain a de base voltage of Vcc/3, a de emitter current of 1 mA, and a de voltage at the collector that allows for ±1-V signal swing at the collector with the minimum collector voltage no lower than Vg. Use a de current in the base 7.7 [25 minutes) The transistor in the emitter follower of Fig. 7.7.1 [21 points] (refer to Figure below) has 100. Assume VBE =0.7 V and neglect the Early effect. (a) Find the de emitter current Ig. [4 points] [1 point] [5 points] (b) Find the value of the emitter resistance re- (c) Find the input resistance Rin- (d) Find the voltage gain from signal source to the [2 points] transistor base, u/sig- (e) Find the voltage gain from transistor base to [3 points] the output, /. (f) Find the overall voltage gain, w/sig- (g) Find the output resistance Rout [1 point] [5 points] = 10 k +5V Rip = R₂ = 10 k Figure 7.7.1 -5V R₁₂-1 k -0%

Fig: 1