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ECE 511: Analog Integrated Circuits

Fall 2023

For the two-stage OTA below, assume that he 30 μA and that all transistors are designed for

|Vel=0.2V. Assume: v=0.5 V for all devices, Vac3V, MS and M7 are 2X larger than MB, A-0.2V².

Mi

Transistors las

Inn

1. Calculate the total power consumption of this OTA.

2. Complete the table below for the small-signal parameters of all transistors.

Vatt

3. What is the gain of this OTA in dia?

4. What is the CMRR of this OTA in da?

3. What is the common-made input range of the circult?

6. What is the output swing of this OTA?

M₂

out

OPI

7. Assume that this OTA has parasitic capacitances C-C-100ff, where is the total shunt

capacitance at output of stage 1 and C; is the same for stage 2. What value of Cc is needed to

set the gain-bandwidth product equal to the second-pole location (resulting in 43-deg phase

margin)?

C, dr

T₂

8. For this value of Cc, calculate the GBW (in MHz, careful of the 2n) and slew rate (in V/us), where

dV

slew rate is defined as SX=²

C₂

9. What value of Rr is needed to set the zero location to the LHP at 1.7X the GBW value?

10. For the values you have selected in Table 1, will this OTA have any systematic offset? Why ar

why not?

Fig: 1