Exercise 3 How many address bits the following memories do require? Answer: This requires.... address bits a. 2 MBytes memory b. 32 Kbits memory Answer: This requires ... address bits c. 64 Mbits memory Answer: This requires ... address bits d. 2 GBytes memory Answer: This requires ... address bits/nExercise 3 1- Is the CPU cortex MO+ Von Neuman or Harvard architecture? Justify your answer and provide refence (datasheet link, with page number) supporting your answer. 2- The memory of the KL25 Microcontroller is shown in the Figure below. Deduce the design of the interface circuit between the CPU (Cortex MO+) and each of the memories shows in the picture (e.g. provide the equation of OutputEnable (OE), connected to each of these memories). Remember that the CPU Cortex MO+ has 32 bits address (A[31:0]) and 32 bits data (D(31:0)). Memory 1 Memory 2 Memory 3 Memory 4 Memory S Memory 6 — System SHIM OxE0100000 Private Piperal Bus MFFFFF External device 1.008 External RAM 1.0GB SRAM Code 0.508 0500 OxFFFFFFFF 0.568 0x0000000 OxFFFFFFF 0x40000000 xFFFFFFF 0x60000000 OxSFFFFFFF 0x40000000 0x3FFFFFFF 0x20000000 0xFFFFFFF 0x00000000

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Exercise 3 How many address bits the following memories do require? Answer: This requires.... address bits a. 2 MBytes memory b. 32 Kbits memory Answer: This requires ... address bits c. 64 Mbits memory Answer: This requires ... address bits d. 2 GBytes memory Answer: This requires ... address bits/nExercise 3 1- Is th