Figure 1 details the VHDL model of a finite state machine (FSM). With reference to this Figure, answer the following questions: a) Identify the number of inputs, number of outputs and number of statesof the FSM.(5 Marks) b) State, with an explanation, if the FSM is of Moore or Mealy type.(3 Marl c) Explain when the state of the FSM will change. d) Draw a state diagram to describe the sequential behaviour of the FSM. e) Explain the purpose of a test bench unit for this FSM, It is NOT necessary to write any VHDL code for a test bench.

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