Figure B1a shows a state diagram for a digital circuit that produces a 3-bit pattern.Assume that a synchronous counter is to be designed that produces the 3-bit output sequence shown in figure B1a.

Write down a state table showing the binary output sequence of the circuit, listed in the same order that they occur on the state diagram. Briefly describe any changes to the state diagram that may be necessary, to make the design realisable. Illustrate your proposed changes by drawing a modified version of the state diagram. Answer the following questions: i.How many D-type flip-flops would you need to implement the modified diagram? ii.How many possible states are needed to be taken into account? iii.What would be the size of the K-map? To avoid the extra work required to solve this problem, instead of solving the original problem, use a simple 4-bit counter which counts from 0 to 9 (white circles shown in Figure B1b), and an encoder to map the counter outputs to the actual states (blue rectangles shown in Figure B1b).

Assuming that the 4-bit counter is already available and designed, make use of K-maps simplification technique, and obtain minimised sum of products Boolean equations describing the Encoder. To do that, consider the counter values (while circles in Figure B1b) as input in K-map and assume that any unused states can be treated as 'don't-care' states. Write down the equations in your answer book and attach the K-maps and draw the circuit diagram of the encoder. Use the following block instead of the counter:

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