Question

Figure B3a shows the logic diagram for 4-bit shift register with D flip-flop while figureB3b shows a timing diagram of the 'Clock' and input data 'Din' waveforms.

Write an HDL Verilog code to describe the circuit in Figure B3a. Note that the circuit has three inputs: Din, Clock and Reset; and one output Qout. Given that the serial input data-bits applied to 'Din' change state 'just after' the-positive-edges of the 'Clock' signal, sketch the waveform for the output of flip-flop'FF3', 'Qout' (Figure B3b).

Write down a general expression for the delay between 'Din' and the nth flip-flop 'Q'output, 'Qn', in terms of 'n' and the period of the clock, 'Tclk', rounded to the nearest whole number of clock periods. If the clock frequency used to drive the circuit shown in figure B3b is 2.5MHz,calculate the maximum delay that can be introduced by the circuit and state whichoutput the delayed signal would appear on. Using circuit in Figure B3a, and a 2x1 multiplexer with SEL input shown in figureB3c, draw a circuit diagram that can be used as a 4-bit shift register when (SEL = 1)or a 4-bit memory when (SEL = 0).When the circuit is in a shift register mode, it operates the same as circuit in FigureB3a. However, when the circuit is in memory mode, each flip-flop preserves its stateregardless of incoming clock.

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