Implement the following SOP using Both NAND-NAND and NOR-NOR logics (2 separate implementations) A'BC+C'D'+BCD+A'CD' (Assume that the cost is proportional to inputs. A one input NAND/NOR cost is 1x, a 2-input NAND gate's cost is 2x, etc.) Upload your solution showing circuit implementations and costs

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