In this assignment you need to design the control for an automated washing machine in a laundromat.The machine starts when a coin is deposited and an input from the coin sensor received, which will stay on till reset at the end of the cycle. It sequences through the following stages: soak, wash, rinse and spin.There is one timer. You can assume each stage will take the same amount of time. The timer begin sticking as soon as the coin is deposited, generates a signal at the end of the time period, and then resets itself and starts again. If the lid is raised during the spin cycle, the machine stops spinning and goes to the end of the cycle, with the timer reset also. At the end of the cycle the timer and the coin sensor will need to be reset ready for the next user. a) Identify the system inputs and outputs. b) Draw a state diagram for the FSM. c) Determine if the number of states can be reduced and assign them with binary codes. d) Design and implement the FSM using D, T and JK flip-flops. e) Verify the JK flip-flop implementation in (d). f) Write Verilog HDL models for the machine based on the state diagram in (b) and the JK flip-flopsequential circuit that you implement in (d).

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