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Question 33284

posted 1 years ago

1. Write behavioral Verilog code of 4-bit shift register with the functionalities: parallel load (select ==00), shift left (select ==01),shift right (select ==10), and no shift (select ==11). Consider serial input to be 0 in both shifts. Use two select line inputs. (State Machine is not needed)

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Question 33285

posted 1 years ago

2. Write behavioral code for a 2-bit up/down counter. The counter should have synchronous reset. (State Machine is not needed)

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Question 33286

posted 1 years ago

3. Write behavioral code for up/down 2-bit binary counter (same as q2).Use state machine. Show the state machine diagram and implement code that reflects the state machine. Following is a template that you can use-

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