/n/n/n ECE-111 Advanced Digital Design Projects Develop SystemVerilog RTL model for Programmable N-bit Rate ½ Convolutional Encoder: Length should be parameterized, to allow any number; in practice, we'll confine to 3

to 9 In the System Verilog module implement a rate ½ structure for any constraint length value, N You will need two reduction XORs and two bitwise ANDS ● O hint: you may wish to adapt your design from my programmable LFSR Synthesize and simulate using conv. enc. testbench provided Testbench is provided for a 5-bit convolutional constraint length. In the testbench file parameter N can be set to some other value. Review synthesis results (resource usage and RTL netlist/schematic) for N=5. Review input and output signals in simulation waveform. Assume below mentioned primary port names and SystemVerilog RTL module name Ifsr. About Convolutional Encoder : It is like an LFSR, but has data in and data out, rather than any feedback. O For rate ½, we generate two output bits for every input bit, once per clock cycle O It requires very little hardware – build it from simple shift-registers with bitwise AND and reduction xor. N-bit conv. enc. would require N-1 internal flip-flops A convolutional encocer is type of a shift register which performs the following steps: O Masks a sequence using a row of 2-input AND gates each AND[i] outputs MASK[i] & Shift_Reg_Tap[i] O This is done twice in parallel for rate ½ Does a reduction XOR of the outputs of these AND gates Do this twice, once per set of ANDs and tap patterns Outputs these reduction XOR results Shifts the bits in the shift register one position to the right (in our application) Replaces the vacated bit with the value at the data input port O ■ Homework Submission : Submit report (PDF file) which should include: SystemVerilog design and testbench code Synthesis resource usage and schematic generated from RTL netlist viewer Simulation snapshot and explain simulation result to confirm it works as a LFSR O Simulation snapshot can be presented for any one of the N value (say N = 5) Resource usage explanation and post mapping schematic is optional to submit. Note: ■ When creating RTL model for conv. enc., name System Verilog Module name as : conv_enc Assume below mentioned Primary Ports for convolutional encoder O Input clk (clock) O Input reset (asynchronous reset / negedge signal) Input[1:0] load_mask (synchronous and active high signal) Input[N-1:0] mask (gets loaded when load_mask != 0) Input data_in Output[1:0] data_out ο ο ο ο clk data_in reset load_mask[1:0] mask[N-1 :0] CE data_out[0] data_out[1] You should have three interal registers, one for the data history / state, and the other two for the programming mask / XOR tap selections. The reset control affects only the state register, not the two mask registers. If load_mask !0, the history register should hold its current value. It should advance/shift only when reset == 1 and load_mask 0. == Lab7 folder posted on Canvas has CE_testbench.sv testbench code to simulate with CE System Verilog module. It also has a skeletal conv_enc.sv file with primary port list. Students can add implementation code for convoluitional encoder./n Homework-6a: Develop SystemVerilog RTL model for N-bit gray-code to binary value conversion: Value N can be 4. Synthesize code and run simulation using testbench provided Testbench is provided for 4-bit gray to binary value conversion. Review synthesis results (resource usage and RTL netlist/schematic) Review input and output signals in simulation waveform. About Gray Code and Conversion to Binary Value: Gray code named after Frank Gray, is an ordering of the binary numeral system such that two successive numbers differ in only one bit O Gray code was originally designed to prevent spurious output from electromechanical switches Gray codes are widely used to facilitate error correction in digital communication applications ■ G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 O Gray code to Binary Value Conversion MSB of the binary code is always equal to the MSB of the given binary number. Other bits of the output binary value can be obtained by XORing gray code bit at that index and binary bit at next index. Use below mentioned 4-bit Gray code to Binary conversion equation, circuit and truth table as a reference for SystemVerilog code development. 1 1 1 1 1 1 1 1 0 0 0 0 O O O Gray Code Value G2 G1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 1 0 0 ECE-111 Advanced Digital Designs GO 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Value B2 B1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gray Code G3 G2 G1 GO XOR XOR B(3)=G(3) B(2)=G(2) xor B(3) B(1) = G(1) xor B(2) B(0)=G(0) xor B(1) XOR Binary Value B3 B2 B1 ВО Note : when simulating gray to binary code, ensure binary values for given gray code in waveform is reflected as per the truth table above. When creating RTL model for gray code to binary value conversion, name System Verilog Module name as : gray_code_to_binary_convertor Assume below mentioned Primary Ports for gray code to binary convertor Input clk (clock) Input rstn (asynchronous reset / negedge signal) Input gray_value (N-bit input gray code signal) Output binary_value (N-bit output converted binary value signal) clk reset gray_value[N-1:0] gray_code_to _binary_conv ertor binary_value[N-1:0] Note: Testbench for gray_code_to_binary_convertor and empty RTL module with primary ports for design is provided in Lab6/gray_code_to_binary_convertor folder. Homework-6b: Develop SystemVerilog RTL model for N-bit Carry Lookahead Adder : Synthesize code and run simulation using testbench provided Carry Lookahead adder required fulladder logic module. Full adder systemverilog code is provided in labs folder. Testbench is provided for 4-bit carry lookahead adder Review synthesis results (resource usage and RTL netlist/schematic) Review input and output signals in simulation waveform. Carry Look Ahead Adder : A Carry lookahead Adder is made of a number of full adders cascaded together. Carry lookahead adder is similar to ripple carry adder with the difference that it calculates the carry bit before the full adder is done with its operation. Advantage of carry lookahead adders is that it adds two numbers faster than ripple carry adder The drawback is that carry lookahead adder takes more logic. For faster performance when adding two number select carry lookahead adder implementation and for more lower resource usage select ripple carry adder implementation The figure below shows 4 full-adders connected together to produce a 4-bit lookahead carry adder. 4-bit Carry Lookahead Adder C4+ A3 B3 1-bit Full C3 Adder S3 A2 B2 1-bit Full Adder S2 A1 B1 A2 B2 1-bit Full C1 Adder S1 A1 B1 АО ВО Carry Lookahead Logic (generate and propagate carry) ↑ ↑ A3 B3 Generate Carry → G(i) = A(i).B(i) Propagate Carry → P(i) = A(i) + B(i) (called "propagate carry") Carry out → C(i+1) = G(i) + P(i).C(i) 1-bit Full Adder SO AO ВО By pre-computing the carry equation, addition of input values can be generated faster. Below mentioned equations can be used to compute carryout. 8 CO Note: In SystemVerilog code, above mentioned G, P and C formulas should be implemented for Carry generation which represents the gray box in above mentioned diagram. For each stage of full adder, Carryout can be computed independently (no ripple) using G(i), P(i) and C(i+1) formulas. For example for 4-bit carry lookahead adder, lets compute carryout from first stage of AO and BO addition : G(0) = A(0). B(0) P(0) = A(0) + B(0) C(1)=G(0) + P(O).C(O) (Note: C(0) is Carryin to first stage fulladder) Further replacing G(0) and P(0) in C(1) equation we can get : O C(1) = (A(0). B(0)) + (A(0) + B(0)).C(0) O Note : Carryout, C(1) is dependent on AO, BO, CO (same as Cin) values which are known upfront. Hence as the first stage full adder is adding AO and BO, Carryout can be generated simultaneously using above mentioned equation. Similary, C(2), C(3), C(4) formulas can be created which would be function of known values of A, B and Cin inputs. Refer to youtube video on CarryLook Ahead Adder for further understanding : https://youtu.be/6kTdgkbYZqA When creating RTL model for carry lookahead adder, name System Verilog Module name as : carry_lookahead_adder Assume below mentioned Primary Ports for carry look ahead adder Inputs A and B (these are values to be added using carry look ahead adder logic) Input CIN (carryin to first stage of fulladder instance in carry look ahead adder) Output result (result of A[N-1:0] + B[N-1:0] + CIN) O Note: Output signal result MSB bit includes final stage fulladder carryout A[N-1:0] B[N-1:0] CIN carry lookah ead_adder result[N:0] Note: Testbench for carry_lookahead_adder and empty RTL module with primary ports for design is provided in Lab6/carry_lookahead_adder folder. Homework-6c: Develop SystemVerilog RTL model for Clock divide by 3 Synthesize code and run simulation using testbench provided Testbench is provided for clock divide by 3 Review synthesis results (resource usage and RTL netlist/schematic) Review input and output signals in simulation waveform. See below reference snapshot for expected output clkout signal. Note: As shown in diagram below clkout signal period is 3 times clkin signal period. Wave - Default clkin reset ckout 0 Msgs Sto Sto Assume below mentioned Primary Ports for clock divide by 3: Input clkin (input faster clock which needs to be divided) Input reset (synchronous reset and high reset) Output clkout (3 times divided clkout signal) clkin clkout is 3 times slower than clkin reset clock_divide_ by_3 clkout Note: Testbench for clock_divide_by_3 and empty RTL module with primary ports for design is provided in Lab6/clock_divide_by_3 folder.