Problem 2. [30 pts] Simulation Simulate the circuit in Problem 1. In this simulation, you would need to do the following: 。 Body terminal of a transistor should be connected to its Source to avoid body effect. 。 Set all the capacitors to very large value, for example, 1 F. ■In LTspice you should put only "1" in the cap value because F (Farad) is already the default unit of capacitance. If you add "1 F" in the value, LTspice will interpret it as 1 fF which is too small. ⚫ For Vsig, use a voltage source with AC Amplitude value set to 1. To acquire bias condition, you should perform .op simulation and report ID, VG, VD and VS. • To acquire gain for each stage, you should perform .ac simulation using decade sweep (and not linear sweep) and use the plot Expression to plot VG/Vsig, Vo/VG, and Vo/Vsig- ■ The frequency sweep in the .ac simulation should be from 1 Hz to 10 GHz. Show the screen-capture of results with highlighted results for the following parameters: a. Include a screen short of the simulated schematic. b. M1: report ID1, VG1, VD1 and VS1. c. DC voltage at Vout d. Gain: VG/Vsig, Vo/VG, and va/Vsig. This should be a Bode plot. e. Apply a sinusoidal signal at the input with amplitude of 10 mV and frequency of 1 kHz, full signal plot VG and Vo. f. Following e, increase the amplitude until the output voltage is distorted (i.e., the output is not a good sinusoidal waveform anymore). Compare this amplitude value with question (i) in Problem 1 and give a brief comment what happens.

Fig: 1