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Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3..QO', are cleared to logic-0 asynchronously, by asserting the 'Rst' input.With 'Rst' at logic-0, the counter outputs change on the positive-edge of the 'Cik'input. Upon reaching output state = <1, 0, 0, 0>, the counter returns to state <0, 0, 0, 1> and repeats the sequence as long as 'Rst' is negated. (a)Design a synchronous counter to implement the behaviour shown in table B2a,making use of the flip-flop shown in figure B2a (assume that clear (CLR) inputs is active-high). Fully record all design steps and draw a labelled logic diagram of your design.

The counter designed in part (a) is to be described using the Verilog-HDL. ListingB2a below shows an incomplete description of the counter.Making use of module-instantiation statements.

Fill in the missing text (indicated by the dotted lines) required to complete thedescription of the counter.

Write down a sequential block to generate a continuous clock on signal 'Clk', given-the declarations:

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