Use a two-input multiplexer circuit with D-Type flip flops to design a 4-bit parallel loaded right shifting shift register circuit.(6 marks) (b) Complete the timing diagram provided in Figure 3 for the parallel loaded right shifting shift register circuit you designed in part (a).(8 marks) (c)For a negative edge trigger J-K flip flop with Preset and clear inputs, complete Q in Figure 4.(6 marks) (d)For a D-type flip-flop with active low Preset and Clear, indicate on the separate provided diagram, the state of the Q output after each clock pulse on the receipt of the D input in Figure 5, identifying the modes of operation. Assume positive edge triggerоperation.(5 marks)

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