2. A BCD adder that adds four BCD digits and produces a sum digits in BCD is shown in the figure below. a) Write a Verilog model that describes this

BCD adder in structural style using Verilog HDL primitives. b) Write a Verilog model that describes this BCD adder using Verilog HDL data flow modeling c) Write a test bench and use Modelsim to verify if the models in 1.a and 2.b work as four BCD digits adder. (Test bench and simulation are required to verify the BCD adder functionality)