IV. a) Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter( R). Annotate the gate width

with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. b) Sketch equivalent circuits for the falling output transition. c) Sketch the equivalent circuit for worst case rising output transition. d) If R is the resistance of unit nMOS transistor and C is its capacitance, findTpdf and Tpdr for 3-input NOR gate if the output is loaded with 5 identicalNAND gates. 2) An output pad contains a chain of inverters to drive the large off-chip capacitance. If the off chip capacitance is 20pF and the first inverter has a capacitance of 40fF, how many inverters are needed to drive the load with least delay? Estimate this delay.