3. A demultiplexer, also known as data distributor, takes in a single input and distributes over several outputs. A demultiplexer of 2^n outputs has n select lines. a. Write a Verilog User Defined Primitive (UDP) to model a 1-to-4 demultiplexer. b. Use the 1-to-4 demultiplexer designed in 2.a to design a 1-to-16 demultiplexer. C. Write a Verilog model that describes a 1-to-16 demultiplexer using Verilog HDL data flow modeling d. Write a test bench and use Modelsim to verify the functionality of the 1-to-16 demultiplexer models in 2.b and 2.c.

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