3. Step: 3a - The heart of the mini-project. VM24 Only - Due Sunday, 4/7 by 11:59pm Design the microarchitecture interpreter for executing/interpreting the above macro-program by: a. First, design the virtual hardware (Level 1) - CPU - for executing each micro-architecture instruction based on the Instruction Set given to you below. The design of your virtual machine (CPU) would be a pseudocode in C, C++, or Java programming language. Your virtual machine should include all the necessary registers and other data structures needed for the task. (See the instruction set and instruction format in section 4, and the types of special and general-purpose registers referenced in the above assembly code.) b. The OS machine level (sitting on top of your ISA-level) would be a driver', a pseudocode of the master program, that simply allocates space (RAM memory) for the various parts of the program listed in section 2 above. (The OSML doesn't accomplish much, at this point - no fancy memory management or scheduling, or synchronization - since you have only one program/job's execution to simulate.) c. All the variables, registers, etc. in the driver and the virtual CPU define the state of the VM24 computer. For example, the PC is part of the state. Therefore, it is instructive to define a data structure, called PCB (process control block) to maintain the state of the computer. The following schematic, for the VM24 architecture, is a simple guide for you to design and implement each component of the architecture. Note: You have a choice between C, C++, or Java for the pseudocode. The focus is on the OS driver, the CPU and its components, the RAM (skip the 'Disk') and have the Loader load the 'microprogram' into the RAM. [Note: the 32-bit microinstructions will assist in the instruction 'Decode' stage.] Step 2b above should guide you in getting the Decoder's logic right. The Execute will serve as the ALU (made of functions', or opcodes) which will 'interpret' each instruction of the program listed in the Assembly/Hex form. The Long-Term and the Short-Term/Dispatch components are not needed, except the PCB which carries the 'state' of the VM24. There will be no "Context-Switching in this exercise. C Pr/nDecode (info) (0) Fech CPU PC+1 PC=0 PC РСВ 1d 8-23 State 8 19 080 OS driver Scheduler 10 Execute (para) Opcode...... [memory (info)] Program File 00000 Long scheduler disk Loader Effective_addr) //JOB 1EB 2C15212 25 words ABCDEFA person Instruct data 02C12345 Data BCC 2 DATA portion END Job #2 JOB 2 CF 19 (: 3 2048 job1 job 2 0-18 (memory) RAM 2 1 1024 8 PCBi Short Scheduler dispatcher Context Switch RQ 2 1 4-byte word (8 hex-chars) copy 16 PCBI CPUI г2 General Purpose Cpu reg PCREG register Г1 PC2

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