A. Design a code in Verilog HDL and create the symbol of the ALU unit based on the following table.

B. Add the designed components symbol and connect it to the previous designed components in the block diagram, as explained in the figure below.

C. Create and insert 2x1 Multiplexer (16-bits input width) to cover the two expected values of the second ALU operand, as shown in the above figur. D. Create waveform (University program VWF) to simulate and verify your block diagram. Your waveform should show the correct ALU result based on the fetched instruction.