(a) Why III-V materials are studied as channel alternatives for an n-FET in the future CMOS technology? What are the challenges when compared to a Si channel n-FET? Write an

explanation not longer than 200 words. (b) Why the InxGa1-xAs channel is fabricated on an insulator? Which advantages this technological solution brings to the n-FET in CMOS for digital applications? Write your answer using a maximum of 200 words. [6 marks](c) Estimate a threshold voltage at low and high drain biases from the ID-VG characteristics for the In As-Ol MOSFET in Fig. 3. How this compares with the value given in Fig. 5? Do you have an agreement with the DIBL? (d) Explain what a subthreshold slope (S.S.) is. Comment on the sub-threshold slope of InAs-OI MOSFET and Ino.53Gao.47AS-OI MOSFET in a comparison with the Intel Si tri-gate FET and the gate-all-around (GAA) FET by Purdue shown in Fig. 10.The explanation should not be longer than 200 words.