Consider the following parameters for the transistors in fig 1. VDS,sat_n=VDS, sat_p=0.25 V, Vtn=0.972 V, Vtp|=0.748 V, unCox=4.954e-05 A/V² and upCox=2.549e-05 A/V². (Assume long channel devices). a) [2 pts.] Consider the CMOS input stage shown in fig 1. (loads of diff pairs are not shown). What Vds value would you choose for MR2 and Vsd for MRI for max headroom operation? b) [8 pts.] Based on your Vds and Vsd choices in part (a), find an appropriate voltage range for each of the bias voltages Vbl & Vb2 (al<Vbl<bl & a2<Vb2<b2) such that the tail current devices operate properly, i.e. find al, bl, a2, b2. c) [10 pts.] Modify the ranges that you got in part (b) to be 1.15*al<Vbl<0.85*b1 and 0.85*a2<Vb2<1.15*b2, and based on these new ranges, size (find W/L) MR1 and MR2 such that their drain current is 10μA, choose Vbl and Vb2 such that your W/L choices are optimized for the best CMRR response vs. frequency response. d) [10 pts.] Size (find W/L) M1, M2, M3 and M4 such that the maximum value of the total gm of this stage is 100 µA/V. Assume that gm of the n-diff pair is equal to gm of the p-diff pair. e) [4 pts.] State one benefit of such a circuit over regular diff amps.

Fig: 1