Consider the following sequence of instructions to compute x+y+xy for two parallel vectors V8 and VI. where x in ve and y

in VI:

addvv.d V2, V, VI

multv.d V3, V8, V1

addvv.d V4, V2, V3

Assume that we have a vector processor with one vector multiplication unit whose latency is 7 and one vector addition

unit whose latency is 6.

Let n=32 represent the length of the vector supported on our processor. The processor has fully-pipelined vector execution

units. The vector processor supports chaining. How long would it take the original loop to execute on this processor?

a. 32 cycles

b. 120 cycles

c. 200 cycles

d. 52 cycles

e. 150 cycles

f. 100 cycles

g. 48 cycles

h.76 cycles

L 74 cycles