C3 [5/15/10/10] We begin with a computer implemented in single-cycleimplementation. When the stages are split by functionality, the stages do notrequire exactly the same amount of time. The original

machine had a clock cycletime of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5ns; EX, I ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns. What is the clock cycle time of the 5-stage pipe lined machine? If there is a stall every 4 instructions, what is the CPI of the newmachine? What is the speedup of the pipelined machine over the single-cycle machine? d. [10] If the pipelined machine had an infinite number of stages, whatwould its speedup be over the single-cycle machine?