machine had a clock cycletime of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5ns; EX, I ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns. What is the clock cycle time of the 5-stage pipe lined machine? If there is a stall every 4 instructions, what is the CPI of the newmachine? What is the speedup of the pipelined machine over the single-cycle machine? d. [10]
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