Question

Figure B1 shows a digital circuit of a frequency divider. The D-type flip-flops used in the circuit are positive-edge triggered and have active-high asynchronous set and reset inputs (labelled 'S' and 'R', unconnected inputs are assumed to be logic-0). Assuming that the 'Reset' input is pulsed to logic-1 initially, and the 4-bit switch input' SW is set to '0000', determine the sequence of states appearing on the <Q3, Q2,Q1, Q0> outputs of the flip-flops. Hence draw a state diagram to illustrate the sequence, with the state values (Q) shown in decimal (Q3 is the MSB). Write down Verilog-HDL statements to describe the 4-bit equality comparator, that compares input 'SW' with the flip-flops states <Q3, Q2, Q1, Q0>', using the following: continuous assignment statement ii. primitive gates Ignore the <' and >' outputs on the symbol and make the following assumptions: The signal 'Pulse' is a module output. The flip-flop 'Q' outputs are declared as single-bit wires. The input 'SW is a 4-bit bus port. (C)Given the following module header for the D-type flip-flops used in Fig. B1, write down a complete Verilog-HDL source description for the circuit shown in Fig. B1. The top-level input/output ports are shown coloured blue in Fig. B1 (the 'x' indicating the number of bits), and the bus labelled 'Q' represents the 4 flip-flop outputs <Q3,Q2, Q1, Q0>. Connect any unused flip-flop inputs to logic-0. (d)With reference to the state diagram drawn in part (a), determine the division ratio(number of clock pulses per output pulse) of the output pulses appearing on 'Pulse' ifthe 4-bit input switches 'SW are set to 4'b1001 in Fig. B1.  Fig: 1  Fig: 2  Fig: 3  Fig: 4  Fig: 5  Fig: 6  Fig: 7  Fig: 8  Fig: 9  Fig: 10  Fig: 11  Fig: 12  Fig: 13  Fig: 14

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