uCox/2 (UA/V2)
Vth (V)
Lambda (V¹)
(for L-0.5um)
Cgdo (F/m)
Cjo (F/m²)
NMOS
120
0.5
0.15
2x10-10
103
Vad = 2.5V
Phi = 0.7V (built in potential of pn junction)
Cjo=0 bias capacitance of pn junction
Gate dielectric: SiO2, 10nm thick
PMOS
40
-0.5
0.2
2x10-10
103
0.7V
2.5V
6. Source to bulk capacitance for the NMOS. Note: the area of a source or drain is
device width times 0.5um.
Fig. 1
1.5V
Calculate the following both for the NMOS and PMOS transistors in the inverter circuit
shown (Fig.1). The gate widths are 2um and lengths are 0.5um. The voltage at each node is
marked. Note the N-well is at Vdd.
Fig: 1