Question 1 An essential part of a BCD adder is a comparator that compares a 4-bit input vector and outputs a '1' if the input vector is larger than "1001". The

truth table for this is given here: . Input vector 0000 0001 . 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output vector 0 0 0 0 0 0 0 0 0 0 Design a VHDL entity that models this function. The architecture description can be of any type, structural, behavioral, or other (hint: you also can use a "with s select" structure). Simulate your design and show correct beaviour for ALL input vectors. Organize your simulation so that the input vector is displayed in decimal form. Upload the following for this question: Your complete VHDL source code that includes the ENTITY and ARCHITECTURE section A Screenshot of the correct simulation 1 1 1 1 1 1 [25 marks]