Question 3 BILE ->12->0->1->2₂ Design a modulo-13 counter, a counter that counts from 0 to 12 (0->1->2->3. and provide the simulation result. The counter has a two input signals and one

output: • Besetn: this signal resets the counter "0000" when Resetn = '0' . Clock: this is the clock input; the counter increases by every positive edge of Clock Z: this is 4-bit vector which outputs the count value Upload the following for this question: Your complete VHDL code that includes the ENTITY and ARCHITECTURE description A screenshot of the simulation result which clearly shows correct behaviour. . . [25 marks]