Question 4 Design an FSM in VHDL that does the following: . . . ● . . The FSM has three inputs: Besetn, Clock, and w The FSM has one output z Reseto resets the FSM to the starting state if Besetn = '0' The FSM advance to the next state on each rising edge of the clock signal Clock if during four immediately preceding clock cycles the input w was equal to '1'. Otherwise, the value of z is equal to '0' Upload the following: . w is an asynchronous input signal The output signal z is equal to Rosst Clock Your complete VHDL source code, i.e. the ENTITY and ARCHITECTURE description A screenshot of a simulation that shows correct behaviour. Use the following template for the input signals: hh nthuhuh n [25 marks]

Fig: 1