Semiconductor devices: p-n junctions 1. A GaAs wafer has a variation in electron concentration across the wafer. The electron concentration drops from 1018 cm3 to 1016 cm³ across a distance of 2 um. The electron mobility of GaAs at room temperature is 8500 cm²V-¹s1. a) Using the Einstein relation, calculate the diffusion constant for GaAs at room temperature. b) What is the current density due to electron diffusion in the GaAs wafer?

4. For each of the following use a Karnaugh map to produce the minimal product of sums. For each shade each distinguished 0-cell. Also, if more than one possible minimal answer is possible, give the possible answers. \text { a. } \quad J a(a, b, c)=\prod(1,2,5,6) \text { b. } \quad J \mathrm{~b}(a, b, c, d)=\prod(1,3,5,7,13,15) \text { c. } \quad J c(a, b, c, d)=\prod(1,3,6,9,11,12,14) \text { d. } \quad \mathrm{Jd}(a, b, c, d)=\sum(0,1,2,5,8,10,13) \text { map in 1's but circle 0's }

IV. a) Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter( R). Annotate the gate width with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. b) Sketch equivalent circuits for the falling output transition. c) Sketch the equivalent circuit for worst case rising output transition. d) If R is the resistance of unit nMOS transistor and C is its capacitance, findTpdf and Tpdr for 3-input NOR gate if the output is loaded with 5 identicalNAND gates. 2) An output pad contains a chain of inverters to drive the large off-chip capacitance. If the off chip capacitance is 20pF and the first inverter has a capacitance of 40fF, how many inverters are needed to drive the load with least delay? Estimate this delay.

4.Find V, for the circuit in Figure 3. State all assumptions made.

4. This question is similar to one of your homework assignments. A page of the TLE2201 data sheet is provided at the last page of this quiz. This op amp will be used over the frequency range of 1 kHz to 10 kHz at room temperature, with a gain of 40 dB as shown in the circuit below. The output voltage is 0 dBV (1V). What is the total voltage noise of the circuit? What is the signal-to-noise ratio in dB? Show your calculation. (20 points)

5.17 For comparison, find the capacitance ratio (MOS Vs PN junction) : CMOS/CPN [20 points] Hint: For MOS, use the breakdown voltage of 10 V to find oxide thickness. For PN junction, use reverse bias voltage of 5V.

1. Name two elemental semiconductors, three III-V semiconductors, one ll-VI semiconductor, and one III-V alloy.

4. Find the output voltage Vo equation in terms of Vs . Use the diode equation with the diode current to derive the equation. (Hint: Perform node voltage analysis at the inverting terminal of the OpAmp using the diode equation for the current through D1)

Table B2 shows the output sequence of a synchronous counter. The counter outputs, 'Q3QO', are initialised to the value <o, 1, 1, 0> asynchronously, by asserting the 'Reset' input. With 'Reset at logic-0, the counter outputs change on the positive-edge of the 'CK input. Upon reaching output state <Q3, Q2, Q1, Q0> = <0, 0, 1, 1>, the counter returns to state <0, 1, 1, 0> and repeats the sequence, as long as 'Reset' is atlogic-0 Draw a state diagram for the synchronous counter, representing the state values in decimal format. Any unused states can be assumed to be 'don't care' states. Write down the decimal values of any 'don't care' states. (4 marks)Design a synchronous counter to implement the behaviour shown in table B2,making use of T-type flip-flops with positive-edge sensitive clock inputs and activehigh set (S) and reset (R) inputs. Fully record all design steps and draw a labelled logic diagram of your design.

An electronic device is made of of InGaAs compound semiconductor which is forming a P+ N junction. P+ and N side has doping concentration of10^20/cm^3 and 10^17/cm^3 respectively. Now answer the following questions: