3 a) Sketch energy-band diagrams for the p-n junction under forward bias and under reverse bias. b) Sketch an I-V graph to show the current-voltage characteristics of a p-n junction under forward bias and reverse bias.

5.17 For comparison, find the capacitance ratio (MOS Vs PN junction) : CMOS/CPN [20 points] Hint: For MOS, use the breakdown voltage of 10 V to find oxide thickness. For PN junction, use reverse bias voltage of 5V.

\text { c) } 10 \text { Use the Mean Square Error Criterion }\left(\mathbf{E}(\mathbf{b})=\mathbf{T} \sum\left[\mathbf{y}(\mathbf{k})-\left.\mathbf{u}(\mathbf{k})\right|^{2}\right)\right. \text { to find } E(b) for k = 0,1,2,3,..,0 in terms of the constant b where T = sampling time=1 second in this part, i.e. t = k.

4. Find the output voltage Vo equation in terms of Vs . Use the diode equation with the diode current to derive the equation. (Hint: Perform node voltage analysis at the inverting terminal of the OpAmp using the diode equation for the current through D1)

Table B2 shows the output sequence of a synchronous counter. The counter outputs, 'Q3QO', are initialised to the value <o, 1, 1, 0> asynchronously, by asserting the 'Reset' input. With 'Reset at logic-0, the counter outputs change on the positive-edge of the 'CK input. Upon reaching output state <Q3, Q2, Q1, Q0> = <0, 0, 1, 1>, the counter returns to state <0, 1, 1, 0> and repeats the sequence, as long as 'Reset' is atlogic-0 Draw a state diagram for the synchronous counter, representing the state values in decimal format. Any unused states can be assumed to be 'don't care' states. Write down the decimal values of any 'don't care' states. (4 marks)Design a synchronous counter to implement the behaviour shown in table B2,making use of T-type flip-flops with positive-edge sensitive clock inputs and activehigh set (S) and reset (R) inputs. Fully record all design steps and draw a labelled logic diagram of your design.

An electronic device is made of of InGaAs compound semiconductor which is forming a P+ N junction. P+ and N side has doping concentration of10^20/cm^3 and 10^17/cm^3 respectively. Now answer the following questions:

In the circuit shown below, find the power delivered by the current source

Silicon is doped with phosphorus to a density of 10 21'm* A) What are the majority and minority carriers? B) Calculate n, p and the position of EF (this must be measured relative to the edge of either the conduction or valence band, whichever is more convenient). C) What is the probability that states at the edge of the conduction band and valence band are occupied? D) Repeat the first part (A+B) for material doped with boron to the same density. E) How does the position of the Fermi level depend on doping?

4. For each of the following use a Karnaugh map to produce the minimal product of sums. For each shade each distinguished 0-cell. Also, if more than one possible minimal answer is possible, give the possible answers. \text { a. } \quad J a(a, b, c)=\prod(1,2,5,6) \text { b. } \quad J \mathrm{~b}(a, b, c, d)=\prod(1,3,5,7,13,15) \text { c. } \quad J c(a, b, c, d)=\prod(1,3,6,9,11,12,14) \text { d. } \quad \mathrm{Jd}(a, b, c, d)=\sum(0,1,2,5,8,10,13) \text { map in 1's but circle 0's }

1. Consider a MOS (Metal Oxide Semiconductor) interface with the following parameters: -Oxide dielectric thickness = 3.5nm; relative dielectric constant (€) = 20 -Semiconductor doping (p type) = 10%/cm³ A. Plot the low frequency (1Hz) normalized* capacitance vs. voltage characteristics for the above MOS structure (ideal case) B. Plot the low frequency (1Hz) normalized* capacitance vs. voltage characteristics for the above MOS structure assuming an interface state density (D) = 10¹/cm² at the dielectric/semiconductor interface (spread uniformly through the Silicon band gap) C. For the MOS interface (with D = 10"/cm²), plot the it normalized* capacitance vs. voltage characteristics for 3 different doping values: 10%/cm³, 10¹/cm³, and 10%/cm³. D. For the MOS interface (with D = 10"/cm²), plot the normalized* capacitance vs. voltage characteristics for 3 different oxide thickness: 3.5nm, 5nm, 6nm (er = 20 for all three cases)