2. Consider the following circuit that contains a Trojan circuitry shown in red. Assume that the inputs are statistically independent and have a 50/50 chance of being a logic one.

3- Design a 2-to-1 multiplexer by using UDP. The select signal is s, inputs are i0, i1, and the output is out. If the select signal s = x,the output out is always 0. If s = 0, then out = 10. If s = 1, then out = i1.

Write down a Verilog-HDL primitive gate instance corresponding to the waveform in figure A3, assuming A and B are inputs and F is the output?

3) (3 points) A 2-bit counter has the following excitation equations: Do = Qo,D₁ = Q₁Q0

Figure A12 shows a repeating clock waveform. Write down a complete initial sequential block to generate the signal 'CLK'.

1- What type of delay model is used in the following circuit? Write the Verilogdescription for the module Y. b- calculate the longest path delay ?

Task 7.3 Draw the logic circuit corresponding to the minimised NAND-NAND function you obtained in Task 7.2 using SN74AC00N (which has 4 x 2 input NAND gates) and 74HC20N (which has 2 x 4 input NAND gates). As mentioned in the example at the start of the lab, this diagram should give all the information that is necessary should another person wish to build it on the NI myDAQ without reference to any other documents. You will lose marks if any information is not supplied.

The diagram below shows a JK flip-flop comprising a D-type positive-edge triggered flip-flop, two AND gates, an OR gate and an inverter. By including an extra input ("J" and "K" compared to just "D") the JK provides more opportunities for logic minimisation than the D-type. The JK used to be the preferred flip-flop as it offers better opportunities for logic minimisation. With the advent of high levels of circuit integration this has been eclipsed in popularity by the D-type which offers advantages in terms of reduced design complexity.

Q.5 Reduce the following functions to their minimum sum of products form. Show all of your working. X= ABCD + ABCD + ABCD + ACD + ABCD Marks) (10 Marks) X= ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD (15 L

Objectives: To study the operation and usefulness of several MSI code devices. converter and adder circuit