2. Consider the following circuit that contains a Trojan circuitry shown in red. Assume that the inputs are statistically independent and have a 50/50 chance of being a logic one.

4. The authors of the USB Trojan article considered USB channels that support devices such as speakers and keyboards to be especially vulnerable. Why?

5. The following problems are based on the following paper that we discussed in class: C. Lamech, R. M. Rad, M. Tehranipoor, and J. Plusquellic, "An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities," Information Forensics and Security, IEEE Transactions on DOI - 10.1109/TIFS.2011.2136339, vol. 6, no. 3, pp. 1170-1179, 2011. Consider the following frequency data (in GHz) collected for 10 different ring oscillators on 8 different chips. (An excel spreadsheet with the same data is also available in the homework folder for you to download.)

6. Consider a RO like the one drawn in Figure 3 of the Lamech paper. Assume that the delay through an inverter is 20 picoseconds and the delay through the NAND gate is 30 ps. What is the expected frequency of oscillation for this ring oscillator?

9. Another paper we read was: Xuehui Zhang and M. Tehranipoor, "Case study: Detecting hardware Trojans in third-party digital IP cores," in Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium on, 2011, pp. 67-70. a) What kinds of coverage analysis may be used by verification engineers to determine if their simulations have done an adequate job of verification. How can these coverage numbers be used by verification engineers to try to identify suspected Trojans? b) What methods were used by the authors of this paper to reduce the number of suspicious signals? Describe them.

PART 1: SHOW ME ONE GATE FROM EACH OF THESE CHIPS. AND GATE [7408] OR GATE [7432] NOT GATE[7404] NAND [7400] NOR [7402] XOR [7486] PART 2: SKIP PART 3: NOR FROM NAND OR FROM NAND AND FROM NAND NOT FROM NAND XOR FROM NAND PART 4: A. CONNECT ALL 6 NOT GATES ON YOUR 7404 AND SHOW HOW EACH NOT GATE WORKS. B. CALCULATE HOW LONG THE TIME IS FOR EACH SET OF GATES TO GO

4. Simplify below Boolean expression.

2. Proof the simplification rule (a) x+x'•y=x+y (b) x (x'+y)=x-y

EXPERIMENT : DIGITAL LOGIC GATES AND K- MAP Lab Report

3. Write the Boolean expression of the below schematic of x and complete the timing diagram of x

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