1. A Trojan writer must ensure that his/her Trojan circuitry is not likely to be detected during manufacturing test, and thus understanding how test works is important. Consider the following circuit.

Deduce the sequence generated by the four-stage linear feedback shift register that has a feedback function given by Q2 + Q3 with the initial stages of: Qo=1, Q₁ =1, Q2 =1 and Q3 = 1.

10. Derive the state table and draw the state diagram for the state machine circuit shown below. Note that this is very similar to Fig. 5.17 in the textbook but uses a T flip-flop rather than a D flip- flop.

9. (Similar to 5.12 in Mano 5th Edition) For the state table from Problem 8, a. Derive the reduced state table. b. Draw the state diagram corresponding to the reduced state table.

8. (Similar to 5.12 in Mano 5th Edition) For the following state table, draw the corresponding state diagram.D

7. Simulate the circuit from problem 6 with the "count" wire represented by a clock. Simulate enough clock transitions to demonstrate the ripple counter moving through all possible states from '0000' to '1001' and starting over again.

1. Design a block diagram simulation of a 6-bit serial shift register. Your answer to this problem is your schematic. The 4-bit version from the lecture is shown below. Place an output pin at the output of each flip-flop and name them Qo - Q5

4. Design a block diagram simulation of a 3-bit ripple counter using T flip-flops. Your answer to this problem is your schematic. The 4-bit version from the lecture is shown to the right. Name the outputs from each flip-flop Q1, Q2, Q4, respectively, indicating their binary place.

3. Assume the use of two 4-bit shift registers performing a serial transfer. The schematic from the lecture is given below. Given the table of initial values for Shift Register A and B, fill in the remaining values at each time instant.

2. Create this waveform: input the following sequence to your circuit from problem 1: a zero followed by '11' and then all zeroes after that. Show that the '11' sequence propagates through the flip-flops in the simulation. The clock can be left on the entire time until the '11' sequence disannears after reaching the last flip-flop output