Table B2 shows the output sequence of a synchronous counter. The counter outputs, 'Q3QO', are initialised to the value <o, 1, 1, 0> asynchronously, by asserting the 'Reset' input. With 'Reset at logic-0, the counter outputs change on the positive-edge of the 'CK input. Upon reaching output state <Q3, Q2, Q1, Q0> = <0, 0, 1, 1>, the counter returns to state <0, 1, 1, 0> and repeats the sequence, as long as 'Reset' is atlogic-0 Draw a state diagram for the synchronous counter, representing the state values in decimal format. Any unused states can be assumed to be 'don't care' states. Write down the decimal values of any 'don't care' states. (4 marks)Design a synchronous counter to implement the behaviour shown in table B2,making use of T-type flip-flops with positive-edge sensitive clock inputs and activehigh set (S) and reset (R) inputs. Fully record all design steps and draw a labelled logic diagram of your design.

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