The diagram below shows a JK flip-flop comprising a D-type positive-edge triggered

flip-flop, two AND gates, an OR gate and an inverter. By including an extra input ("J"

and "K" compared to just "D") the JK provides more opportunities for logic

minimisation than the D-type. The JK used to be the preferred flip-flop as it offers

better opportunities for logic minimisation. With the advent of high levels of circuit

integration this has been eclipsed in popularity by the D-type which offers

advantages in terms of reduced design complexity.