ts 40 Here is a block diagram for the register file: 32X64 WP Register File Ra Rb Rw Bus W Cik Bus A Upload Choose a File Bus B RegWr Save

your new register file as RegisterFile.v. Test your code against the provided testbench to make sure it is working (If you are not working on Vivado, you may need include "RegisterFile.v" command). Demo for your TA. Attach a zip/tar file containing your completed module along with a screenshot of the waveform. registerfile tb.v↓/n2023 cements 5 ents ons ro 1.3 40 Question 1 Implement a 32x64 register file (32 registers; each register is 64-bit wide). Below is a specification of the register file: • Inputs Ra and Rb are read register indices. Input Ra indexes the register whose value is on BusA, and input Rb indexes the register whose value is on BusB. • Input Rw is the write register index. • When RegWr is high, the data on Bus W is stored in the register specified by Rw, on the negative (falling) clock edge. Register reading should occur after the register write (on the negative clock edge), but before the positive clock edge. • Register 31 must always read zero, even if it has not been written to. • The Register File module should have the following interface: ●. module RegisterFile (BusA, BusB, BusW, RA, RB, RW, RegWr, Clk); output [63:0] BUSA; output [63:0] BusB; input [63:0] BusW; input [4:0] RA; input [4:0] RB; input [4:0] RW; input RegWr; input clk; reg [63:0] registers [31:0]; Here is a block diagram for the register file: Ra Bb 20 pts ----- Bus A