Which of the following statements are true about a Set-Reset latch made with NOR gates? (Select all that apply.) If Set=1 and Reset3D0 the output Q of the latch will be set, Q=1. O If Set=1 and Reset-D1 an illegal state isproduced. OThe set-reset latch is an asynchronous device. O If Set=0 and Reset=1 the output Q of the latch will be cleared or reset, Q=0.