Problem 5: Consider the circuit in Figure 5. This

is called a self-biased inverter. The resistor R,

forces the gates and the drains of the transistors to

be at the same voltage.

Large signal behavior: Ignore channel length

modulation and assume that

W

Vout

n

VDD

Mp

M₁

M

W

Q.-C.)

(a) Identify the range of values of VDD (between 0

Figure 5

and 1.8V) over which both transistors are ON

and in saturation. Do NOT assume that the threshold voltages are the same.

Small signal behavior: Consider channel length modulation for the small signal model.

(b) For the chosen transistor sizing, show that gm,n=gm,p.

(c) Calculate the small signal gain, Av.

the Vin

(d) Calculate the input impedance, Rin.

(e) Calculate the output impedance, Rout.

For parts (c) through (e), express your answer symbolically i.e. in terms of parameters

gm,n, Io,n, fo,p, etc.

(f) What is the peak-to-peak amplitude of the largest sinusoidal voltage allowed on the

output node without pushing either transistor out of saturation? Express it

symbolically, in terms of VDD, VTH,n, VTH,p etc.

(5+2+3+4+3 + 3 = 20 points)