Consider the following sequence of instructions to compute x+y+xy for two parallel vectors V8 and VI. where x in ve and y in VI: addvv.d V2, V, VI multv.d V3, V8, V1 addvv.d V4, V2, V3 Assume that we have a vector processor with one vector multiplication unit whose latency is 7 and one vector addition unit whose latency is 6. Let n=32 represent the length of the vector supported on our processor. The processor has fully-pipelined vector execution units. The vector processor supports chaining. How long would it take the original loop to execute on this processor? a. 32 cycles b. 120 cycles c. 200 cycles d. 52 cycles e. 150 cycles f. 100 cycles g. 48 cycles h.76 cycles L 74 cycles

2) What does “ROM" mean and how is it used in computers? Please provide several examples.

When designing a display unit for one hexadecimal digit they have found out that a particular pixel should light (represented by a high signal, i.e. a 1) for the following digits: 5, 7, a, b, d, e, f.The hexadecimal digits are given by the four signals x0, x1, x2, x3, which encodes the digit \left(\pi 3^{2} \pi 1 \pi\right) 2 Find a logic diagram with a minimal number of gates that gives the right signal for this pixel.

Consider the following algorithm: what values are printed out when the user provides number1=9, and number2=20? Explain each of the pseudocode keywords given in the above algorithm. c) Provide a flow diagram representing the above algorithm.

Consider the below assembly code and assume that all memory locations below EA=490A0 store values (35)16, and higher addresses have (45)16 stored. DS=4000; DI=90A0; DX-0000 (initially) MOV AX, 5678 MOV BX, 1232 ADD AX, BX MOV CX, [DI+8] ADD DX, AX The content of Register AX, DX after execution of the above code is: O AX = (5678)16 and DX = (0000)16 AX = (68AA)16 and DX = (68AA)16 AX = (AA68)16 and DX = (68AA)16 O AX = (68AA)16 and DX = (0000)16

Consider the below assembly code and assume that all memory locations below EA=490A0 store values = (35)16, and higher addresses have (45)16 stored.

9 Consider a machine with 32-bit virtual addresses and 32-bit physical addresses. Thememory is byte-addressable. In paging of memory, a process has the page tablebelow, and the page size is 512 bytes. Assume that the first address in Page 0 is 0and the first address in Frame 0 is 0, and each byte is addressable. The following addresses are given in Base 10. 9.1 What is the physical address corresponding to logical address 532? 9.2 What is the physical memory address corresponding to the logical address 1038?

The address (002C)16 in the Interrupt Vector Table (IVT) refers to the following entry: O a. (44)10 b. (20)10 Oc. none of the above O d. (11)10 e. (02)16

5. (16 points) Consider deadlock avoidance with single resources. Assuming we have 4 process P1,P2, P3, P4. and 4 resources r1, r2, r3, r4. Consider all| 4 processes are writers (i.e. no resources can be shared among processes). Suppose the processes are to acquire and release the release the resources in the following order (and assume the OS has the complete knowledge of the schedule beforehand) – we only show the first 8 requests. if a request is denied, the process immediately quits and release all resources it is holding/waiting (if any). if a process have to wait for a resource (if another process is holding it), the avoidance algorithm can still grant the request and allow that process to wait all waiting queues for each resources are FIFO a.Draw the resource allocation graph before the first request is made b. Will the third request (P3 request r3) be granted? Explain your answer using the resource allocation graph. c. Is there any request after that one that will be denied? If so, show the first request that will be denied and explain why using the resource allocation graph. If not, show the request allocation graph at the of the 8-th request.

For a particular branch with this observed behavior: NTNNNINN What is the prediction accuracy of a 2-bit dynamic predictor? Assume the predictor starts in the 01 (weakly N) state. The answer should be formatted as a decimal, so 20% accuracy should be represented as .2.