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2. (15 pts) Assume that individual stages of the datapath have the following latencies: ALU/Logic Jump/Branch Load Store 20% 15% IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps 45% 20% (a) Left table: If you can add two more pipeline registers in addition to the five existing stages of the left table, where would you put the first and the second one? After that, what will be the critical path delay? (b) Looking at the right table, what is the percent instructions using "immediate generation" unit? (c) What percent of all instructions use instruction memory?

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