3.12 Trace the behavior of an edge-triggered D flip-flop using a master-servant design (see Figure 3.25) for the input pattern in Figure 3.99. Assume each internal latch initially stores a 0. Complete the timing diagram, assuming logic gates have a tiny but nonzero delay. D/Dm Cm Qm/Ds Cs Qs Figure 3.99 Edge-triggered D flip-flop input pattern timing diagram.

Fig: 1