3. For the input shown below, show the flip flop outputs. a. Assume that the flip flop is a D flip flop without a clear or preset. b. Assume that the flip flop is a D flip flop with an active low clear. c. Assume that the flip flop is a D flip flop with active low clear and preset inputs. d. Assume that the flip flop is a 7 flip flop with the same input as part a, and that Q is initially 0. e. Assume that the flip flop is a 7 flip flop with an active low clear and the same inputs as part b. Clock Dor T b. and e. CLR' c. CLR' PRE'

Fig: 1