5. Practice Exercises

5.1 Multiplexer

Design and implement an 8-1 Multiplexer using a case

statement.

5.2 Array Adder

Design and implement an Array Adder. Depending on an input

bit named 'op', if:

• op is 1: Add together two integer arrays with addition and

stores the result in a third array.

• op is 0: Subtract one integer array from the other and store

the result in a third array.

You can assume all three arrays are hardcoded as signals.

5.3 Array-Mapped Increment

Design and implement an Array-Mapped Increment circuit that

takes an integer named "x" as input and adds "x" to all

elements in an integer array. If an array value exceeds 9, that

array element is reset to zero. You may assume that the integers

are hardcoded signals.

6. Deliverables

Practical demonstration of the sample exercises will be

requested during the lab and instructor may ask for their code

to be submitted on Moodle. Complete work of the practice

exercises must be submitted on Moodle by the specified

deadline. Provide the following for all designs:

1. Complete VHDL code.

2. Flow Summary and Successful Compilation.

3. RTL Viewer.

4. Power Consumption.

5. ModelSim simulation for the designs.