5. Practice Exercises

5.1. FSM

Design and implement the following finite state machine with the rising edge of the clock with a 1-bit input

that the next state depends on. The FSM does not have a reset button, and only when at state S3 and the input

has the value of zero, your system will go back to S0.

0

5.2. 32-bit Adder

start

1

S2

0

1

Figure 3. FSM diagram for task 5.1

1. Complete VHDL code.

2. Flow Summary and Successful Compilation.

3. RTL Viewer,

4. Power Consumption.

5. Maximum Frequency Analysis.

6. ModelSim simulation for the designs (except 32-bit Adder).

S1

S4

Design and implement a 32-bit adder using Generate of smaller size bit adders. Analyze and evaluate your

design.

6. Deliverables

Practical demonstration of the sample exercises will be requested during the lab and instructor may ask

for their code to be submitted on Moodle. Complete work of the practice exercises must be submitted on

Moodle by the specified deadline. Provide the following for all designs: