6. [10 pts] Below circuit is a S-R latch which uses NOR gates. Design a S-R latch using NAND gates and provide a truth table for the S-R latch. S R [S-R latch] P Q S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 [Truth Table] Q+ 0 1 0 0 1

Fig: 1