6. Consider the following multi-level combinational logic circuits. (a) Implement the circuit given in Figure 1 using only NAND gates (use of inverters is OK) (b) Implement the circuit given

in Figure 1 using only NOR gates (use of inverters is OK) (c) Implement the circuit given in Figure 2 using only NAND gates (use of inverters is OK) (d) Implement the circuit given in Figure 2 using only NOR gates (use of inverters is OK)